SkypeIn: 916.740.1117

Cell: 530.210.6832

Email: sidney@blueforestlabs.com

Web: www.blueforestlabs.com

Sidney Rhodes, Founder

Blue Forest Labs, LLC

 

ASIC Design Engineer

FPGA Artist

 

Roseville, CA 95678

 

 
Text Box: Blue Forest Labs ® FPGA Design Revolutionized.

Blue Forest Labs Design Services

 

FPGA Design — BFL will start from your requirements to define, document, implement and verify an FPGA design to suit your needs.

 

High Bit-Rate Designs — Timing closure is key to high bandwidth, high bit rate LVDS and SERDES based FPGA interconnects. BFL has expertise in this area as well as in implementing high speed clocks internal to the FPGA.

 

RTL Design and Simulation — Your logic design can be generated using either Verilog or VHDL and targeted for ASIC, FPGA or both.

 

ASIC Emulation — Emulate your ASIC as it is being designed by paralleling its development with FPGAs.  RTL updates from the ASIC design process can be ported on demand to the FPGA(s) and new FPGA bit images made available to you.

 

FPGA IP Core Development — Independent development or co-development of FPGA IP cores for subsequent licensing.

 

Debugging — Logic analyzer probes can be inserted into the FPGA designs to allow real time monitoring of internal signals as you would during simulation.

 

Availability — Long or Short term consulting, onsite or remote.